The present invention relates to semiconductor technologies, and more particularly to methods for the fabrication of semiconductor devices.
As the critical dimensions shrink in metal oxide semiconductor field effect transistor (MOSFET), the short channel effect (SCE) has become a critical issue. FinFET (Fin Field Effect Transistor) has good gate control capability to effectively suppress the short channel effect. Therefore, FinFET devices are often used in the design of small semiconductor devices.
However, due to the reduced size, the device is prone to punch-through effect. In order to suppress the punch-through effect, a channel stop ion implantation is often carried out in the bottom of the fin. However, for N-type metal oxide semiconductor (NMOS) devices, channel stop impurity ions can easily spread during annealing, resulting in loss of well implanted ions. Therefore, a greater ion implantation dose in channel stop ion implantation is often required in the NMOS devices.
However, the inventors have found that, after annealing, the greater implantation dose can cause the implanted ions to diffuse into the P-type metal oxide semiconductor (PMOS) device, so that the N-type fin becomes P type, thus affecting the performance of the device. The problem is particularly severe in small fins in SRAM (Static Random Access Memory), in which N-type and P-type FinFET devices are disposed adjacent to each other.